Synopsys Timing Constraints And Optimization User Guide 2021

The guide focuses on the creation and application of Synopsys Design Constraints (SDC). SDC is the industry-standard format used to convey the design intent—specifically timing, area, and power requirements—to synthesis and static timing analysis (STA) tools.

: Methods for specifying set_input_delay and set_output_delay to model external interface requirements. synopsys timing constraints and optimization user guide 2021